1. Field of The Invention
The present invention relates generally to a synchronous semiconductor memory device wherein a data transfer is carried out in synchronism with a clock. More specifically, the invention relates to an internal data transfer system in a DDR synchronous DRAM and so on wherein a pre-fetch system for a plurality of bits of data is used.
2. Related Background Art
Conventionally, in order to realize a rapid data access and high data band width in DRAMS, synchronous DRAMs (SDRAMs) are proposed. The SDRAMs are practicable from 4-Mbit DRAMS, and account for most of the current 64-Mbit DRAMs. The SDRAMs are characterized in that a rapid access time and cycle time are realized by utilizing a clock synchronization. Recently, it is requested to further accelerate the SDRAMs.
The operating speed of an SDRAM is determined by a series of data transfer operations for transferring data, which are read out to bit lines of a memory cell array, to a main data line via a column selecting gate to amplify the transferred data to transfer the amplified data to an input/output terminal via a peripheral data line. There is a limit to the accelerating of the data transfer operations. Therefore, as a technique for apparently improving a data transfer speed, there is a system for dividing a column access path into 2, 3 or 4 pipeline stages in accordance with the number of CAS latencies to carry out the overlap operation of these pipeline stages. In addition, a plurality of bits of data per I/O terminal are simultaneously read from the memory cell array to be parallel-to-serial converted by a peripheral circuit to be fetched. This technique is called a data pre-fetch, which will be hereinafter referred to as a 2-bit pre-fetch when 2-bit data per I/O terminal are simultaneously read out, and as a 4-bit pre-fetch when 4-bit data per I/O terminal are simultaneously read out.
In the case of the 2-bit pre-fetch, 2-bit data parallel-transferred to a data line via a column selecting line are amplified by data line buffers, respectively, to be transferred to separate peripheral data lines. The order in which the 2-bit data parallel-transferred to the peripheral data lines are fetched is determined in accordance with the least significant column address A0, so that the 2-bit data are parallel-to-serial converted to be fetched.
At present, the main current of the clock frequencies of SDRAMs is in the range of from 100 MHz to 133 MHz. If the above described data pre-fetch system is adopted by a technique for carrying out a column selection in a clock cycle to synchronize output data with both of leading and trailing edges of a clock or synchronize output data with an intersecting time between a clock CLK and a complementary clock /CLK thereto, it is possible to realize a data transfer speed of 200 MHz to 266 MHz twice as large as the clock frequency (DDR SDRAM).
However, there is always a limit to the chip size in DRAMs. In particular, when a pre-fetch system is adopted, there is a problem in that a peripheral wiring region is pressed. For example, in the 2-bit pre-fetch, the number of peripheral data lines is twice as large as that when any pre-fetch systems are adopted. In the case of an SDRAM for reading data to 16 input/output terminals in parallel, the number of required peripheral data lines is 32, and in the case of 32-bit parallel readout, the number of required peripheral data lines is 64.
If the capacity of a memory is further increased like a 256-Mbit memory, the rate of the area occupied by a memory cell array increases, so that the influence of the increased number of peripheral data lines is relatively decreased. However, in a memory capacity of 64 Mbits or 128 Mbits, the area occupied by the peripheral data lines can not be ignored, so that there is a default-like overhead with respect to a conventional DRAM which does not adopt the pre-fetch system.